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| SJ/T 10566-1994 Testability bus -Part 1:Standard test access port and boundary scan architecture (English Version) |
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Detail of SJ/T 10566-1994
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Introduction of SJ/T 10566-1994
本标准规定了数字集成电路和模拟/数字混合集成电路的数字部分用的测试存取口（TAP）与边界扫描结构。本标准规定的测试逻辑可包含在集成电路内，由一个边界扫描寄存器和若干其它块构成，并可通过测试存取口进行存龋本标准适用于在集成电路组装在一块印制电路板或其它基底上后测试集成电路间的互连性、测试集成电路本身和在这个器件正常工作期间观测或修改电路的动作。
Contents of SJ/T 10566-1994