QC/T 1217-2024 Automotive wired high-speed media transmission-Multi-gigabit full-duplex system Technical requirements and test methods (English Version)
QC/T 1217-2024 Automotive wired high-speed media transmission - Multi-gigabit full-duplex system - Technical requirements and test methods
1 Scope
This document specifies the technical requirements and test methods for multi-gigabit full-duplex systems for automotive wired high-speed media transmission.
This document is applicable to multi-gigabit full-duplex systems for automotive wired high-speed media transmission consisting of forward nodes, backward nodes and wiring harness connecting these nodes.
2 Normative references
The following normative documents contain provisions which, through reference in this text, constitute provisions of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.
IEC 60958 Digital audio interface
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
forward direction
transmission direction with a higher rate in wired transmission
3.2
forward node
logical unit with the functions of forward transmission and backward reception
3.3
backward direction
transmission direction with a lower rate in wired transmission
3.4
backward node
logical unit with the functions of backward transmission and forward reception
3.5
link setup time
time taken for a node to transition from entering the link negotiation state to entering the data transmission state
4 Abbreviations
For the purposes of this document, the following abbreviations apply.
ACK: Acknowledge
AES: Advanced Encryption Standard
CA: Certificate Authority
CK: Cipher Key
CMAC: Cipher-based Message Authentication Code
CTR: CounTeR
Gb/s: Gigabitper second
GCM: Galois/Counter Mode
GPIO: General Purpose Input/Output
HMAC: Hash-based Message Authentication Code
I2C: Inter-integrated Circuit
ID: Identification
IK: Integrity Key
MAC: Message Authentication Code
Mb/s: Million bit per second
MDI: Media Dependent Interface
MHz: Million Hertz
NACK: Negative Acknowledgment
NRZ: Non-return to Zero Code
PAM4: 4 level Pulse Amplitude Modulation
PLDB: Physical Layer Data Block
PSD: Power Spectrum Density
PSK: Pre-shared Key
QoS: Quality of Service
RAW: RAW Image Format
RGB: Red/Green/Blue Image Format
RS-FEC: Reed Solomon Forward Error Correction
SoC: System on a Chip
SPI: Serial Peripheral Interface
UART: Universal Asynchronous Receiver/Transmitter
YUV: Luminance and Chrominance Image Format
5 Technical requirements
5.1 Protocol stack
The protocol stack used for forward and backward transmission between forward node and backward node shall comply with Figure 1. The protocol stack shall include a physical layer and a media encapsulation layer. The physical layer and media encapsulation layer shall meet the relevant requirements of Annex A.
Note: To simplify the description, in subsequent clauses, unless specially limited, nodes are used to refer to both forward nodes and backward nodes.
Figure 1 Protocol stack of multi-gigabit full-duplex system for automotive wired high-speed media transmission
5.2 Node state
The nodes shall have power off, power on, link negotiation, link training, data transmission and test states. The node states shall meet the relevant requirements of A.1.
5.3 Transmission rate
The forward transmission shall support forward rate gears 1, 2, 3 and 4 as specified in Table 1, and may support forward rate gears 4a, 5, 5a and 6. If the forward transmission supports the 8Gb/s transmission rate, it shall first support forward rate gear 5a, and on this basis, may support forward rate gear 5. Pre-emphasis technology may be used for forward transmission, as described in Annex B. The backward transmission shall support the backward rate gear 1 as specified in Table 2.
Note: The transmission rate described in this document refers to the physical layer transmission rate.
Table 1 Forward transmission rates
Table 2 Backward transmission rates
5.4 Connectivity
The nodes shall have automatic connection and automatic restoration functions.
When a node is initially configured for data transmission mode, after being powered on, it shall automatically transition from the power-on state to the data transmission state via link negotiation state and link training state. The link setup time shall be less than or equal to 100ms. When a forward node is in the negotiation state and receives a link negotiation request frame, it shall output a link negotiation start signal. When a node enters the data transmission state, it shall output forward and backward data transmission enable signals.
When a node is in the data transmission state, if the forward node or backward node is powered off and then powered on again, it shall automatically restore to the data transmission state.
When a node is in the data transmission state, if the wiring harness connecting the node is disconnected and then reconnected, it shall automatically restore to the data transmission state.
5.5 Bit error rate
Both the forward node and the backward node shall have the function of counting the transmission bit error rate when in the data transmission state. The bit error rate at the receiving end for both forward and backward transmission shall be less than or equal to 10-12.
5.6 Wiring harness fault diagnosis
The nodes shall have wiring harness fault diagnosis function. The wiring harness fault diagnosis function shall be able to correctly determine the type of wiring harness fault and locate the fault position.
When the wiring harness is a coaxial cable, the wiring harness fault types shall include open circuit and short circuit.
When the wiring harness is a twisted pair, the wiring harness fault types shall include single-wire open circuit, double-wire open circuit, wire-wire short circuit, and wire-ground short circuit.
The positioning error for the wiring harness fault shall be less than or equal to ±1m.
5.7 Electrical indexes
The electrical indexes for forward and backward transmission signals shall include the signal eye diagram, power spectrum density, maximum output droop, clock frequency offset, and clock jitter, and shall meet the relevant requirements of A.2.8.
6 Test methods
6.1 Test environment
6.1.1 General
Test environment 1 specified in 6.1.2 shall be used for each test item in 6.2, 6.3 and 6.4, and test environment 2 specified in 6.1.3 shall be used for each test item in 6.5.
The test environment temperature shall be (25±2)℃.
6.1.2 Test environment 1
Test environment 1 shall meet the requirements of Figure 2. The forward node and backward node shall be connected using a wiring harness. The upper computer shall have the functions of configuring the forward and backward nodes and reading measured values and statistical data. When the connecting harness is a shielded twisted pair, its length shall be 10m. When the connecting harness is a coaxial cable, its length shall be 15m. The electrical indexes of the channel between the forward node and the backward node are specified in Annex C.
Figure 2 Test environment 1
6.1.3 Test environment 2
Test environment 2 shall meet the requirements of Figure 3. The upper computer shall have the functions of configuring the node under test and reading the state of the node under test. The electrical indexes of the forward and backward transmission signals shall be measured using an oscilloscope. The test point shall be the transmitting connector end of the chip of the node under test, and the trace length of the board from the chip transmitting pin of the node under test to the connector shall not exceed 30mm.
Figure 3 Test environment 2
6.2 Connectivity
6.2.1 Automatic connection
6.2.1.1 Test procedure
The test procedure for system connectivity is as follows:
a) initially configure the node for data transmission mode, and set the forward rate gear to the gear to be tested;
b) power on the forward node and backward node;
Contents
Foreword i
1 Scope
2 Normative references
3 Terms and definitions
4 Abbreviations
5 Technical requirements
5.1 Protocol stack
5.2 Node state
5.3 Transmission rate
5.4 Connectivity
5.5 Bit error rate
5.6 Wiring harness fault diagnosis
5.7 Electrical indexes
6 Test methods
6.1 Test environment
6.2 Connectivity
6.3 Bit error rate
6.4 Wiring harness fault diagnosis
6.5 Electrical indexes
Annex A (Normative) Transmission protocols
A.1 Node state
A.2 Physical layer
A.3 Media encapsulation layer
A.4 Information security
A.5 Register
Annex B (Informative) Transmission pre-emphasis
Annex C (Informative) Channel electrical indexes
C.1 Channel
C.2 Wiring harness
C.3 MDI
Bibliography
Figure 1 Protocol stack of multi-gigabit full-duplex system for automotive wired high-speed media transmission
Figure 2 Test environment 1
Figure 3 Test environment 2
Figure A.1 Node state machine
Figure A.2 Link negotiation process
Figure A.3 Link training process
Figure A.4 Forward node sending process
Figure A.5 Backward node sending process
Figure A.6 Node signal sending method and sampling point positions for maximum output droop test
Figure A.7 Backward node periodical sends sleep heartbeat frames
Figure A.8 Process of exit from sleep state
Figure A.9 Physical layer processing flow
Figure A.10 Format of 66B block
Figure A.11 Format of forward PLDB
Figure A.12 Forward RS-FEC encoding
Figure A.13 RS symbol interleaving scheme
Figure A.14 Format of forward transmission frame
Figure A.15 Structure of forward scrambling shift register
Figure A.16 PAM4 9B/10B encoding process
Figure A.17 Format of backward PLDB
Figure A.18 CRC linear feedback shift register
Figure A.19 Backward RS-FEC encoding
Figure A.20 Format of backward transmission frame
Figure A.21 Structure of backward scrambling shift register
Figure A.22 Example of physical layer priority transmission
Figure A.23 Example of forward physical layer retransmission
Figure A.24 Example of backward physical layer retransmission
Figure A.25 Scrambling method of the link negotiation frame
Figure A.26 Format of link training frame
Figure A.27 Scrambling method of the link training frame
Figure A.28 Format of synchronization frame
Figure A.29 Scrambling method of the synchronization frame
Figure A.30 Scrambling method of the sleep heartbeat frame
Figure A.31 Eye diagram mask for forward differential signal
Figure A.32 PSD mask for NRZ modulated forward differential signal
Figure A.33 PSD mask for PAM4 modulated forward differential signal
Figure A.34 PSD mask for backward differential signal
Figure A.35 Format of media encapsulation packet with media access control field
Figure A.36 Format of media encapsulation packet without media access control field
Figure A.37 Format of Type A media encapsulation packet
Figure A.38 Forma of Type B media encapsulation packet
Figure A.39 Format of Type C media encapsulation packet
Figure A.40 Format of media encapsulation packet for image service
Figure A.41 RAW8 pixel mapping mode
Figure A.42 RAW10 pixel mapping mode
Figure A.43 RAW12 pixel mapping mode
Figure A.44 RAW14 pixel mapping mode
Figure A.45 RAW16 pixel mapping mode
Figure A.46 RAW20 pixel mapping mode
Figure A.47 RAW24 pixel mapping mode
Figure A.48 YUV420 8 bit even-numbered line pixel mapping mode
Figure A.49 YUV420 8 bit odd-numbered line pixel mapping mode
Figure A.50 YUV420 10 bit even-numbered line pixel mapping mode
Figure A.51 YUV420 10 bit odd-numbered line pixel mapping mode
Figure A.52 YUV420 12 bit even-numbered line pixel mapping mode
Figure A.53 YUV420 12 bit odd-numbered line pixel mapping mode
Figure A.54 YUV422 8 bit pixel mapping mode
Figure A.55 YUV422 10 bit pixel mapping mode
Figure A.56 Loosely YUV422 10 bit pixel mapping mode
Figure A.57 YUV422 12 bit pixel mapping mode
Figure A.58 RGB666 pixel mapping mode
Figure A.59 Loosely RGB666 pixel mapping mode
Figure A.60 RGB888 pixel mapping mode
Figure A.61 RGB10-10-10 pixel mapping mode
Figure A.62 RGB12-12-12 pixel mapping mode
Figure A.63 RGB565 pixel mapping mode
Figure A.64 Format of IEC 60958 media encapsulation packet
Figure A.65 IEC 60958 frame carried in service data
Figure A.66 Format of media encapsulation packet for control service
Figure A.67 Example of address pair and port pair
Figure A.68 Example of I2C transparent mode
Figure A.69 Example of non-transparent mode
Figure A.70 Format of media encapsulation packet for I2C transparent transmission
Figure A.71 Format of media encapsulation packet for control read-write and state acknowledgement
Figure A.72 Format of encapsulation packet for I2C/SPI port control write
Figure A.73 Format of encapsulation packet for UART port control write
Figure A.74 Format of encapsulation packet for standard register control write
Figure A.75 Format of encapsulation packet for custom register control write
Figure A.76 Format of encapsulation packet for I2C port control read
Figure A.77 Format of encapsulation packet for SPI port control read
Figure A.78 Format of encapsulation packet for standard register control read
Figure A.79 Format of encapsulation packet for custom register control read
Figure A.80 Format of media encapsulation packet with state code as write succeeded
Figure A.81 Format of media encapsulation packet with state code as write failed
Figure A.82 Format of media encapsulation packet with state code as read succeeded-with read data
Figure A.83 Format of media encapsulation packet with state code as read failed-without read data
Figure A.84 Format of media encapsulation packet with state code as read failed-with read data
Figure A.85 Format of media encapsulation packet in GPIO oversampling mode
Figure A.86 Format of media encapsulation packet for GPIO trigger mode
Figure A.87 Format of media encapsulation packet for GPIO fixed delay trigger mode
Figure A.88 Example of transmission in GPIO fixed delay trigger mode
Figure A.89 Format of media encapsulation layer transmission acknowledgement packet
Figure A.90 PSK-based authentication process
Figure A.91 Certificate-based authentication process
Figure A.92 Key architecture for PSK-based authentication
Figure A.93 Key architecture for certificate-based authentication
Figure A.94 Key update process
Figure A.95 Integrity protection process
Figure A.96 Key deduction and algorithm negotiation process for PSK-based authentication
Figure A.97 Key deduction and algorithm negotiation process for certificate-based authentication
Figure A.98 Encryption and decryption process
Figure A.99 Authenticated encryption process
Figure A.100 Format of security message encapsulation packet
Figure B.1 Transmission pre-emphasis/de-emphasis structure
Figure B.2 Schematic diagram for pre-emphasis level
Figure C.1 Schematic diagram for composition of transmission channel
Figure C.2 Insertion loss limit curve of shielded twisted pair channel
Figure C.3 Return loss limit curve of shielded twisted pair
Figure C.4 Insertion loss limit curve of coaxial cable
Figure C.5 MDI insertion loss curve
Figure C.6 MDI return loss curve
Figure C.7 MDI near-end crosstalk curve
Table 1 Forward transmission rates
Table 2 Backward transmission rates
Table 3 Wiring harness diagnostic fault injection method
Table A.1 Node state definition
Table A.2 Definition of 66B block indicator bits
Table A.3 Definition of 66B block sub-indicator bit
Table A.4 Definition of forward PLDB control field
Table A.5 Gear interleaving depth
Table A.6 Definition of backward PLDB control field
Table A.7 CRC check generating polynomial
Table A.8 Format of physical layer control message
Table A.9 Format of forward physical layer retransmission message
Table A.10 Format of backward physical layer retransmission message
Table A.11 Format of link re-setup message
Table A.12 Format of sleep control message
Table A.13 Format of negotiation request frame
Table A.14 Format of negotiation response frame
Table A.15 Format of negotiation end frame
Table A.16 Definition of non-information field of link training frame
Table A.17 Definition of link training frame information field
Table A.18 Synchronization frame transmission interval
Table A.19 Format of forward synchronization frame
Table A.20 Format of backward synchronization frame
Table A.21 Format of sleep heartbeat frame
Table A.22 Forward differential signal voltage swing requirements
Table A.23 Backward differential signal voltage swing requirements
Table A.24 Forward NRZ differential signal eye diagram requirements
Table A.25 Upper limit of PSD for NRZ modulated forward differential signal
Table A.26 Lower limit of PSD for NRZ modulated forward differential signal
Table A.27 Upper limit of PSD for PAM4 modulated forward differential signal
Table A.28 Lower limit of PSD for PAM4 modulated forward differential signal
Table A.29 Upper limit of PSD for backward differential signal
Table A.30 Lower limit of PSD for backward differential signal
Table A.31 Clock frequency requirements
Table A.32 Clock jitter requirements
Table A.33 9B/10B control code table
Table A.34 9B/10B data code table
Table A.35 8B/10B control code table
Table A.36 8B/10B data code table
Table A.37 Definition of media access control field
Table A.38 Definition of service type field
Table A.39 Definition of sub-service type for image service
Table A.40 Definition of line segmentation
Table A.41 Definition of image assistance sub-service type
Table A.42 Definition of RAW image sub-service type
Table A.43 Definition of YUV image sub-service type
Table A.44 Definition of RGB image sub-service type
Table A.45 Definition of audio sub-service type
Table A.46 Definition of number of audio frames
Table A.47 Definition of port
Table A.48 Definition of I2C/SPI/UART sub-service type
Table A.49 Definition of bus state
Table A.50 Definition of opcode for control read-write packet
Table A.51 Definition of state code in state acknowledgement packet
Table A.52 Definition of GPIO sub-service type
Table A.53 Definition of GPIO trigger type
Table A.54 Forward and backward transmission delays in fixed delay trigger mode
Table A.55 Cryptographic algorithm
Table A.56 Definition of security message type
Table A.57 Definition of security message content
Table A.58 Register address space
Table A.59 Device manufacturer identifier register
Table A.60 Device manufacturer product identifier register
Table A.61 Device manufacturer product version register
Table A.62 Standard version register
Table A.63 Node type register
Table A.64 High-speed interface register
Table A.65 I2C interface register
Table A.66 SPI interface register
Table A.67 UART interface register
Table A.68 GPIO interface register
Table B.1 Forward transmission pre-emphasis coefficient
Standard
QC/T 1217-2024 Automotive wired high-speed media transmission-Multi-gigabit full-duplex system Technical requirements and test methods (English Version)
Standard No.
QC/T 1217-2024
Status
valid
Language
English
File Format
PDF
Word Count
48000 words
Price(USD)
1440.0
Implemented on
2025-5-1
Delivery
via email in 1 business day
Detail of QC/T 1217-2024
Standard No.
QC/T 1217-2024
English Name
Automotive wired high-speed media transmission-Multi-gigabit full-duplex system Technical requirements and test methods
QC/T 1217-2024 Automotive wired high-speed media transmission - Multi-gigabit full-duplex system - Technical requirements and test methods
1 Scope
This document specifies the technical requirements and test methods for multi-gigabit full-duplex systems for automotive wired high-speed media transmission.
This document is applicable to multi-gigabit full-duplex systems for automotive wired high-speed media transmission consisting of forward nodes, backward nodes and wiring harness connecting these nodes.
2 Normative references
The following normative documents contain provisions which, through reference in this text, constitute provisions of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document (including any amendments) applies.
IEC 60958 Digital audio interface
3 Terms and definitions
For the purposes of this document, the following terms and definitions apply.
3.1
forward direction
transmission direction with a higher rate in wired transmission
3.2
forward node
logical unit with the functions of forward transmission and backward reception
3.3
backward direction
transmission direction with a lower rate in wired transmission
3.4
backward node
logical unit with the functions of backward transmission and forward reception
3.5
link setup time
time taken for a node to transition from entering the link negotiation state to entering the data transmission state
4 Abbreviations
For the purposes of this document, the following abbreviations apply.
ACK: Acknowledge
AES: Advanced Encryption Standard
CA: Certificate Authority
CK: Cipher Key
CMAC: Cipher-based Message Authentication Code
CTR: CounTeR
Gb/s: Gigabitper second
GCM: Galois/Counter Mode
GPIO: General Purpose Input/Output
HMAC: Hash-based Message Authentication Code
I2C: Inter-integrated Circuit
ID: Identification
IK: Integrity Key
MAC: Message Authentication Code
Mb/s: Million bit per second
MDI: Media Dependent Interface
MHz: Million Hertz
NACK: Negative Acknowledgment
NRZ: Non-return to Zero Code
PAM4: 4 level Pulse Amplitude Modulation
PLDB: Physical Layer Data Block
PSD: Power Spectrum Density
PSK: Pre-shared Key
QoS: Quality of Service
RAW: RAW Image Format
RGB: Red/Green/Blue Image Format
RS-FEC: Reed Solomon Forward Error Correction
SoC: System on a Chip
SPI: Serial Peripheral Interface
UART: Universal Asynchronous Receiver/Transmitter
YUV: Luminance and Chrominance Image Format
5 Technical requirements
5.1 Protocol stack
The protocol stack used for forward and backward transmission between forward node and backward node shall comply with Figure 1. The protocol stack shall include a physical layer and a media encapsulation layer. The physical layer and media encapsulation layer shall meet the relevant requirements of Annex A.
Note: To simplify the description, in subsequent clauses, unless specially limited, nodes are used to refer to both forward nodes and backward nodes.
Figure 1 Protocol stack of multi-gigabit full-duplex system for automotive wired high-speed media transmission
5.2 Node state
The nodes shall have power off, power on, link negotiation, link training, data transmission and test states. The node states shall meet the relevant requirements of A.1.
5.3 Transmission rate
The forward transmission shall support forward rate gears 1, 2, 3 and 4 as specified in Table 1, and may support forward rate gears 4a, 5, 5a and 6. If the forward transmission supports the 8Gb/s transmission rate, it shall first support forward rate gear 5a, and on this basis, may support forward rate gear 5. Pre-emphasis technology may be used for forward transmission, as described in Annex B. The backward transmission shall support the backward rate gear 1 as specified in Table 2.
Note: The transmission rate described in this document refers to the physical layer transmission rate.
Table 1 Forward transmission rates
Table 2 Backward transmission rates
5.4 Connectivity
The nodes shall have automatic connection and automatic restoration functions.
When a node is initially configured for data transmission mode, after being powered on, it shall automatically transition from the power-on state to the data transmission state via link negotiation state and link training state. The link setup time shall be less than or equal to 100ms. When a forward node is in the negotiation state and receives a link negotiation request frame, it shall output a link negotiation start signal. When a node enters the data transmission state, it shall output forward and backward data transmission enable signals.
When a node is in the data transmission state, if the forward node or backward node is powered off and then powered on again, it shall automatically restore to the data transmission state.
When a node is in the data transmission state, if the wiring harness connecting the node is disconnected and then reconnected, it shall automatically restore to the data transmission state.
5.5 Bit error rate
Both the forward node and the backward node shall have the function of counting the transmission bit error rate when in the data transmission state. The bit error rate at the receiving end for both forward and backward transmission shall be less than or equal to 10-12.
5.6 Wiring harness fault diagnosis
The nodes shall have wiring harness fault diagnosis function. The wiring harness fault diagnosis function shall be able to correctly determine the type of wiring harness fault and locate the fault position.
When the wiring harness is a coaxial cable, the wiring harness fault types shall include open circuit and short circuit.
When the wiring harness is a twisted pair, the wiring harness fault types shall include single-wire open circuit, double-wire open circuit, wire-wire short circuit, and wire-ground short circuit.
The positioning error for the wiring harness fault shall be less than or equal to ±1m.
5.7 Electrical indexes
The electrical indexes for forward and backward transmission signals shall include the signal eye diagram, power spectrum density, maximum output droop, clock frequency offset, and clock jitter, and shall meet the relevant requirements of A.2.8.
6 Test methods
6.1 Test environment
6.1.1 General
Test environment 1 specified in 6.1.2 shall be used for each test item in 6.2, 6.3 and 6.4, and test environment 2 specified in 6.1.3 shall be used for each test item in 6.5.
The test environment temperature shall be (25±2)℃.
6.1.2 Test environment 1
Test environment 1 shall meet the requirements of Figure 2. The forward node and backward node shall be connected using a wiring harness. The upper computer shall have the functions of configuring the forward and backward nodes and reading measured values and statistical data. When the connecting harness is a shielded twisted pair, its length shall be 10m. When the connecting harness is a coaxial cable, its length shall be 15m. The electrical indexes of the channel between the forward node and the backward node are specified in Annex C.
Figure 2 Test environment 1
6.1.3 Test environment 2
Test environment 2 shall meet the requirements of Figure 3. The upper computer shall have the functions of configuring the node under test and reading the state of the node under test. The electrical indexes of the forward and backward transmission signals shall be measured using an oscilloscope. The test point shall be the transmitting connector end of the chip of the node under test, and the trace length of the board from the chip transmitting pin of the node under test to the connector shall not exceed 30mm.
Figure 3 Test environment 2
6.2 Connectivity
6.2.1 Automatic connection
6.2.1.1 Test procedure
The test procedure for system connectivity is as follows:
a) initially configure the node for data transmission mode, and set the forward rate gear to the gear to be tested;
b) power on the forward node and backward node;
Contents of QC/T 1217-2024
Contents
Foreword i
1 Scope
2 Normative references
3 Terms and definitions
4 Abbreviations
5 Technical requirements
5.1 Protocol stack
5.2 Node state
5.3 Transmission rate
5.4 Connectivity
5.5 Bit error rate
5.6 Wiring harness fault diagnosis
5.7 Electrical indexes
6 Test methods
6.1 Test environment
6.2 Connectivity
6.3 Bit error rate
6.4 Wiring harness fault diagnosis
6.5 Electrical indexes
Annex A (Normative) Transmission protocols
A.1 Node state
A.2 Physical layer
A.3 Media encapsulation layer
A.4 Information security
A.5 Register
Annex B (Informative) Transmission pre-emphasis
Annex C (Informative) Channel electrical indexes
C.1 Channel
C.2 Wiring harness
C.3 MDI
Bibliography
Figure 1 Protocol stack of multi-gigabit full-duplex system for automotive wired high-speed media transmission
Figure 2 Test environment 1
Figure 3 Test environment 2
Figure A.1 Node state machine
Figure A.2 Link negotiation process
Figure A.3 Link training process
Figure A.4 Forward node sending process
Figure A.5 Backward node sending process
Figure A.6 Node signal sending method and sampling point positions for maximum output droop test
Figure A.7 Backward node periodical sends sleep heartbeat frames
Figure A.8 Process of exit from sleep state
Figure A.9 Physical layer processing flow
Figure A.10 Format of 66B block
Figure A.11 Format of forward PLDB
Figure A.12 Forward RS-FEC encoding
Figure A.13 RS symbol interleaving scheme
Figure A.14 Format of forward transmission frame
Figure A.15 Structure of forward scrambling shift register
Figure A.16 PAM4 9B/10B encoding process
Figure A.17 Format of backward PLDB
Figure A.18 CRC linear feedback shift register
Figure A.19 Backward RS-FEC encoding
Figure A.20 Format of backward transmission frame
Figure A.21 Structure of backward scrambling shift register
Figure A.22 Example of physical layer priority transmission
Figure A.23 Example of forward physical layer retransmission
Figure A.24 Example of backward physical layer retransmission
Figure A.25 Scrambling method of the link negotiation frame
Figure A.26 Format of link training frame
Figure A.27 Scrambling method of the link training frame
Figure A.28 Format of synchronization frame
Figure A.29 Scrambling method of the synchronization frame
Figure A.30 Scrambling method of the sleep heartbeat frame
Figure A.31 Eye diagram mask for forward differential signal
Figure A.32 PSD mask for NRZ modulated forward differential signal
Figure A.33 PSD mask for PAM4 modulated forward differential signal
Figure A.34 PSD mask for backward differential signal
Figure A.35 Format of media encapsulation packet with media access control field
Figure A.36 Format of media encapsulation packet without media access control field
Figure A.37 Format of Type A media encapsulation packet
Figure A.38 Forma of Type B media encapsulation packet
Figure A.39 Format of Type C media encapsulation packet
Figure A.40 Format of media encapsulation packet for image service
Figure A.41 RAW8 pixel mapping mode
Figure A.42 RAW10 pixel mapping mode
Figure A.43 RAW12 pixel mapping mode
Figure A.44 RAW14 pixel mapping mode
Figure A.45 RAW16 pixel mapping mode
Figure A.46 RAW20 pixel mapping mode
Figure A.47 RAW24 pixel mapping mode
Figure A.48 YUV420 8 bit even-numbered line pixel mapping mode
Figure A.49 YUV420 8 bit odd-numbered line pixel mapping mode
Figure A.50 YUV420 10 bit even-numbered line pixel mapping mode
Figure A.51 YUV420 10 bit odd-numbered line pixel mapping mode
Figure A.52 YUV420 12 bit even-numbered line pixel mapping mode
Figure A.53 YUV420 12 bit odd-numbered line pixel mapping mode
Figure A.54 YUV422 8 bit pixel mapping mode
Figure A.55 YUV422 10 bit pixel mapping mode
Figure A.56 Loosely YUV422 10 bit pixel mapping mode
Figure A.57 YUV422 12 bit pixel mapping mode
Figure A.58 RGB666 pixel mapping mode
Figure A.59 Loosely RGB666 pixel mapping mode
Figure A.60 RGB888 pixel mapping mode
Figure A.61 RGB10-10-10 pixel mapping mode
Figure A.62 RGB12-12-12 pixel mapping mode
Figure A.63 RGB565 pixel mapping mode
Figure A.64 Format of IEC 60958 media encapsulation packet
Figure A.65 IEC 60958 frame carried in service data
Figure A.66 Format of media encapsulation packet for control service
Figure A.67 Example of address pair and port pair
Figure A.68 Example of I2C transparent mode
Figure A.69 Example of non-transparent mode
Figure A.70 Format of media encapsulation packet for I2C transparent transmission
Figure A.71 Format of media encapsulation packet for control read-write and state acknowledgement
Figure A.72 Format of encapsulation packet for I2C/SPI port control write
Figure A.73 Format of encapsulation packet for UART port control write
Figure A.74 Format of encapsulation packet for standard register control write
Figure A.75 Format of encapsulation packet for custom register control write
Figure A.76 Format of encapsulation packet for I2C port control read
Figure A.77 Format of encapsulation packet for SPI port control read
Figure A.78 Format of encapsulation packet for standard register control read
Figure A.79 Format of encapsulation packet for custom register control read
Figure A.80 Format of media encapsulation packet with state code as write succeeded
Figure A.81 Format of media encapsulation packet with state code as write failed
Figure A.82 Format of media encapsulation packet with state code as read succeeded-with read data
Figure A.83 Format of media encapsulation packet with state code as read failed-without read data
Figure A.84 Format of media encapsulation packet with state code as read failed-with read data
Figure A.85 Format of media encapsulation packet in GPIO oversampling mode
Figure A.86 Format of media encapsulation packet for GPIO trigger mode
Figure A.87 Format of media encapsulation packet for GPIO fixed delay trigger mode
Figure A.88 Example of transmission in GPIO fixed delay trigger mode
Figure A.89 Format of media encapsulation layer transmission acknowledgement packet
Figure A.90 PSK-based authentication process
Figure A.91 Certificate-based authentication process
Figure A.92 Key architecture for PSK-based authentication
Figure A.93 Key architecture for certificate-based authentication
Figure A.94 Key update process
Figure A.95 Integrity protection process
Figure A.96 Key deduction and algorithm negotiation process for PSK-based authentication
Figure A.97 Key deduction and algorithm negotiation process for certificate-based authentication
Figure A.98 Encryption and decryption process
Figure A.99 Authenticated encryption process
Figure A.100 Format of security message encapsulation packet
Figure B.1 Transmission pre-emphasis/de-emphasis structure
Figure B.2 Schematic diagram for pre-emphasis level
Figure C.1 Schematic diagram for composition of transmission channel
Figure C.2 Insertion loss limit curve of shielded twisted pair channel
Figure C.3 Return loss limit curve of shielded twisted pair
Figure C.4 Insertion loss limit curve of coaxial cable
Figure C.5 MDI insertion loss curve
Figure C.6 MDI return loss curve
Figure C.7 MDI near-end crosstalk curve
Table 1 Forward transmission rates
Table 2 Backward transmission rates
Table 3 Wiring harness diagnostic fault injection method
Table A.1 Node state definition
Table A.2 Definition of 66B block indicator bits
Table A.3 Definition of 66B block sub-indicator bit
Table A.4 Definition of forward PLDB control field
Table A.5 Gear interleaving depth
Table A.6 Definition of backward PLDB control field
Table A.7 CRC check generating polynomial
Table A.8 Format of physical layer control message
Table A.9 Format of forward physical layer retransmission message
Table A.10 Format of backward physical layer retransmission message
Table A.11 Format of link re-setup message
Table A.12 Format of sleep control message
Table A.13 Format of negotiation request frame
Table A.14 Format of negotiation response frame
Table A.15 Format of negotiation end frame
Table A.16 Definition of non-information field of link training frame
Table A.17 Definition of link training frame information field
Table A.18 Synchronization frame transmission interval
Table A.19 Format of forward synchronization frame
Table A.20 Format of backward synchronization frame
Table A.21 Format of sleep heartbeat frame
Table A.22 Forward differential signal voltage swing requirements
Table A.23 Backward differential signal voltage swing requirements
Table A.24 Forward NRZ differential signal eye diagram requirements
Table A.25 Upper limit of PSD for NRZ modulated forward differential signal
Table A.26 Lower limit of PSD for NRZ modulated forward differential signal
Table A.27 Upper limit of PSD for PAM4 modulated forward differential signal
Table A.28 Lower limit of PSD for PAM4 modulated forward differential signal
Table A.29 Upper limit of PSD for backward differential signal
Table A.30 Lower limit of PSD for backward differential signal
Table A.31 Clock frequency requirements
Table A.32 Clock jitter requirements
Table A.33 9B/10B control code table
Table A.34 9B/10B data code table
Table A.35 8B/10B control code table
Table A.36 8B/10B data code table
Table A.37 Definition of media access control field
Table A.38 Definition of service type field
Table A.39 Definition of sub-service type for image service
Table A.40 Definition of line segmentation
Table A.41 Definition of image assistance sub-service type
Table A.42 Definition of RAW image sub-service type
Table A.43 Definition of YUV image sub-service type
Table A.44 Definition of RGB image sub-service type
Table A.45 Definition of audio sub-service type
Table A.46 Definition of number of audio frames
Table A.47 Definition of port
Table A.48 Definition of I2C/SPI/UART sub-service type
Table A.49 Definition of bus state
Table A.50 Definition of opcode for control read-write packet
Table A.51 Definition of state code in state acknowledgement packet
Table A.52 Definition of GPIO sub-service type
Table A.53 Definition of GPIO trigger type
Table A.54 Forward and backward transmission delays in fixed delay trigger mode
Table A.55 Cryptographic algorithm
Table A.56 Definition of security message type
Table A.57 Definition of security message content
Table A.58 Register address space
Table A.59 Device manufacturer identifier register
Table A.60 Device manufacturer product identifier register
Table A.61 Device manufacturer product version register
Table A.62 Standard version register
Table A.63 Node type register
Table A.64 High-speed interface register
Table A.65 I2C interface register
Table A.66 SPI interface register
Table A.67 UART interface register
Table A.68 GPIO interface register
Table B.1 Forward transmission pre-emphasis coefficient
