GB/T 46280.2-2025 Specification for chiplet interconnection interface—Part 2: Protocol layer technical requirements English, Anglais, Englisch, Inglés, えいご
This is a draft translation for reference among interesting stakeholders. The finalized translation (passing thorugh draft translation, self-check, revision and varification) will be delivered upon being ordered.
ICS31.200
CCSL55
National Standard of the People's Republic of China
GB/T46280.2-2025
Specification for chiplet interconnection interface-Part 2: Protocol layer technical requirements
Issued on August 19, 2025 Implementation on March 1, 2026
State Administration for Market Regulation, National Standardization Administration
Contents
Preface
Introduction 1 Scope
2 Normative references
3 Terms and Definitions
4 Abbreviations
5 Protocol layer functional requirements
6 General Transmission Requirements for Interconnection Bus Protocol
6.1 General Principles
6.2 Packet General Format
7 Transmission requirements for AXI bus protocol
7.1 General Principles
7.2 AXI Service Channel Mapping
7.3 Packet Splicing Rules for AXI Service Channels
8 Transmission Requirements for Interconnecting with the HAI Protocol
9 Transmission Requirements for Custom Protocol Interconnection
10 Configuration between different protocols
Specification for chiplet interconnection interface-Part 2: Protocol layer technical requirements
1 Scope
This document specifies the protocol layer functional requirements of the chiplet interconnect interface, the general transmission requirements of the bus protocol, and specifies the interface Transmission requirements for AXI bus protocol, HAI protocol, and custom protocol, as well as configuration between different protocols.
This document applies to the design, manufacture and application of chiplet interconnect interfaces.
2 Normative references
The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T46280.1 Chip Interconnect Interface Specification Part 1: General Principles
GB/T46280.3 Chip Interconnect Interface Specification Part 3: Data Link Layer Technical Requirements
3 Terms and Definitions
The terms and definitions defined in GB/T 46280.1 apply to this document.
4 Abbreviations
The following abbreviations apply to this document.
AXI: Advanced Extensible Interface
CCIX: Cache Coherent Interconnect for Accelerators
CHI: Coherent Hub Interface
CN: Channel Number
CPIF: ChipletPHYInterface
CRC: Cyclic Redundancy Check
CXL: Compute Express Link
ECC: Error Correction Code
FEC: Forward Error Correction
Flit: data block (Flow control unit)
HAI: High bandwidth memory access interface (HighbandwidthmemoryAccessInterface)
PAIF: Protocol Adapter Interface
PCIe: Peripheral Component Interconnect Express
SoC: System on Chip
VC: Virtual Channel
GB/T 46280.2-2025 Specification for chiplet interconnection interface—Part 2: Protocol layer technical requirements English, Anglais, Englisch, Inglés, えいご
This is a draft translation for reference among interesting stakeholders. The finalized translation (passing thorugh draft translation, self-check, revision and varification) will be delivered upon being ordered.
ICS31.200
CCSL55
National Standard of the People's Republic of China
GB/T46280.2-2025
Specification for chiplet interconnection interface-Part 2: Protocol layer technical requirements
Issued on August 19, 2025 Implementation on March 1, 2026
State Administration for Market Regulation, National Standardization Administration
Contents
Preface
Introduction 1 Scope
2 Normative references
3 Terms and Definitions
4 Abbreviations
5 Protocol layer functional requirements
6 General Transmission Requirements for Interconnection Bus Protocol
6.1 General Principles
6.2 Packet General Format
7 Transmission requirements for AXI bus protocol
7.1 General Principles
7.2 AXI Service Channel Mapping
7.3 Packet Splicing Rules for AXI Service Channels
8 Transmission Requirements for Interconnecting with the HAI Protocol
9 Transmission Requirements for Custom Protocol Interconnection
10 Configuration between different protocols
Specification for chiplet interconnection interface-Part 2: Protocol layer technical requirements
1 Scope
This document specifies the protocol layer functional requirements of the chiplet interconnect interface, the general transmission requirements of the bus protocol, and specifies the interface Transmission requirements for AXI bus protocol, HAI protocol, and custom protocol, as well as configuration between different protocols.
This document applies to the design, manufacture and application of chiplet interconnect interfaces.
2 Normative references
The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document.
GB/T46280.1 Chip Interconnect Interface Specification Part 1: General Principles
GB/T46280.3 Chip Interconnect Interface Specification Part 3: Data Link Layer Technical Requirements
3 Terms and Definitions
The terms and definitions defined in GB/T 46280.1 apply to this document.
4 Abbreviations
The following abbreviations apply to this document.
AXI: Advanced Extensible Interface
CCIX: Cache Coherent Interconnect for Accelerators
CHI: Coherent Hub Interface
CN: Channel Number
CPIF: ChipletPHYInterface
CRC: Cyclic Redundancy Check
CXL: Compute Express Link
ECC: Error Correction Code
FEC: Forward Error Correction
Flit: data block (Flow control unit)
HAI: High bandwidth memory access interface (HighbandwidthmemoryAccessInterface)
PAIF: Protocol Adapter Interface
PCIe: Peripheral Component Interconnect Express
SoC: System on Chip
VC: Virtual Channel
