Standard No.:	GB/T 46280.3-2025
English Name:	Specification for chiplet inerconnection interface—Part 3: Data link layer technical requirements
Chinese Name:	芯粒互联接口规范 第3部分：数据链路层技术要求
Chinese Classification:	L55    Microcircuit in general
Professional Classification:	GB    National Standard
Source Content Issued by:	SAMR; SAC
Issued on:	2025-08-19
Implemented on:	2026-3-1
Status:	valid
Target Language:	English
File Format:	PDF
Word Count:	14500 words
Translation Price(USD):	435.0
Delivery:	via email in 1~5 business day

GB/T 46280.3-2025 Specification for chiplet inerconnection interface—Part 3: Data link layer technical requirements English, Anglais, Englisch, Inglés, えいご This is a draft translation for reference among interesting stakeholders. The finalized translation (passing thorugh draft translation, self-check, revision and varification) will be delivered upon being ordered. ICS31.200 CCSL55 National Standard of the People's Republic of China GB/T46280.3-2025 Specification for chiplet inerconnection interface—Part 3: Data link layer technical requirements Released on August 19, 2025 Implementation on March 1, 2026 State Administration for Market Regulation, National Standardization Administration Contents Preface Introduction 1 Scope 2 Normative references 3 Terms and Definitions 4 Abbreviations 5 Data Link Layer Functions 6 Interface 7 CPIF 8 PAIF 9 Configuring Interfaces References Specification for chiplet inerconnection interface—Part 3: Data link layer technical requirements 1 Scope This document specifies the data link layer technical requirements for the chiplet interconnect interface, including: transmission message format, data error detection and correction mechanism control, as well as technical requirements related to link status and power consumption management. This document applies to the design, manufacture and application of chiplet interconnect interfaces. 2 Normative references The contents of the following documents constitute essential provisions of this document through normative references. For dated references, only the version corresponding to that date applies to this document. For undated references, the latest version (including all amendments) applies to this document. GB/T46280.1 Chiplet Interconnection Interface Specification Part 1: General 3 Terms and Definitions The terms and definitions defined in GB/T 46280.1 apply to this document. 4 Abbreviations The following abbreviations apply to this document. ARQ: Automatic Repeat Request (AutomaticRepeatRequest) AXI: Advanced Extensible Interface CHI: Coherent Hub Interface CPIF: ChipletPHYInterface CRC: Cyclic Redundancy Check DEC: Double Error Detection ECC: Error Correction Code FEC: Forward Error Correction Flit: data block (Flow control unit) IO: Input/Output port NRZ: Non-Return to Zero PAIF: Protocol Adapter Interface PHY: Physical layer RX: Receiver SEC: Single Error Detection SoC: System on Chip TX: Transmitter 5 Data Link Layer Functions The data link layer provides reliable data transmission for both communicating parties and should implement the following functions: — Transmission error detection and correction mechanism: CRC generation and verification, retransmission, ECC; — Link state and low-power state switching management; — Transmission message format definition; — Binding of multiple channels to form a link with larger transmission bandwidth. 6 Interfaces 6.1 Flit Format 6.1.1 Flit Data Format The data link layer uses Flit as the data transmission unit, and the upper layer data packet is divided and transmitted with Flit as the smallest unit. The Flit data format is shown in Figure 1.